最近終於有點時間,project 沒有這麼趕了,就打算把這個問題修一下,之前有考慮過就傳進去就好,但是因為也想要可以使用 -j 來加速,以及改進下 output 的目錄結構來減少一些 maintain multiple core debugger script 的工作,就想改成 non-recursive 的結構順便練一下功。
主要碰到的問題有幾個,
- How to collect compile options in sub makefile?
- How to collect sources/headers in sub-directories?
- How to keep original build method? (build sub-dir as lib, then link them all)
[1] http://make.mad-scientist.net/papers/how-not-to-use-vpath/
[2] http://make.mad-scientist.net/papers/multi-architecture-builds/#single
[3] https://www.oreilly.com/library/view/managing-projects-with/0596006101/ch06.html#nonrecursive_make
[4] https://www.oreilly.com/library/view/managing-projects-with/0596006101/ch07.html#managing_programs_and_files
問題 1 & 2 的動作有兩個,一個是如何找到 makefile ,另一個是如何記住 makefile 中的資訊。
找檔案的手法有很多,這次是採用 wildcard 的方式,因為已經知道是在哪些目錄下了,這樣找也挺方便的。
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MKFILE := $(foreach d, $(SUBDIRS), $(wildcard $(D_ROOT)/$(d)/makefile) | |
MKFILE += $(foreach d, $(SUBDIRS), $(wildcard $(D_ROOT)/drivers/$(d)/makefile) |
再來就是如何記住,參考 [3] 的方法,這邊的重點是要記得先宣告參數,
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# in parent makefile | |
ALL_SRC := |
之後在 sub makefile 中就可以把 source 或者是 compile option 累加進 var 中,
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ALL_SRC += $(LOCAL_SRC) |
最後問題 3 的需求,主要的問題是如何跟 make 說有哪些 lib 要 build。這邊因為我是每個 sub makefile 都是一個 lib,所以就可以在每個 sub makefile 中加入下面的 rule,這樣每當 sub makefile 被 include 時,就會為每個 sub makefile 建立這個 rule 來 build 出我要的 lib。
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# OBJS are inside $(D_OBJ) | |
$(LOCAL_LIB): $(C_OBJS) $(A_OBJS) | |
$(AR) $(ARFLAGS) $@ $(patsubst %,$(D_OBJ)/%, $^) |